An Improved Structure and Analysis of Asymmetrical Spacer Nanowire Tunnel Field Effect Transistor

Articles in Press

Document Type : Original Article

Authors

1 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh, India

2 Department of Electronics and Communication Engineering, Graphic Era (Deemed to be University), Dehradun, India

Abstract

This paper presents a novel design and analysis of a Low-k Source side Asymmetrical Spacer Halo doped Nanowire TFET. The utilization of high-k hafnium oxide spacer materials in TFET enhance electrostatic control and minimize short-channel effects in nanoscale devices. However, the performance of dynamic circuits suffers with higher fringe capacitance brought on by high-k spacers. Our method focuses on reducing gate capacitance by optimistic utilization of high-k spacer material. The proposed device is constructed in SILVACO TCAD software and results states that the use of Low-k material as silicon dioxide at the Source-side spacer in halo-doped nanowire TFET design results in significantly reduced gate-capacitance and intrinsic-delay. For this proposed TFET device, the circuit performance of advanced nanowire structure can improve drain current characteristics and analog characteristice.  The proposed device exhibits better performance as compared to other spacer engineering devices. As a consequence, the suggested device appears as a strong suitable device for low power digital applications.

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References

  1. Howldar S, Balaji B, Srinivasa Rao K. Investigation and Analysis of Dual Metal Gate Overlap on Drain Side Tunneling Field Effect Transistor with Spacer in 10nm Node. International Journal of Engineering, Transactions B: Applications. 2024;37(5):887-95. 10.5829/ije.2024.37.05b.07
  2. Howldar S, Balaji B, Srinivasa Rao K. Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2023;36(12):2137-44. 10.5829/ije.2023.36.12c.01
  3. Howldar S, Balaji B, Srinivasa Rao K. Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2024;37(3):520-8. 10.5829/ije.2024.37.03c.09
  4. Rohith Sai K, Girija Sravani K, Srinivasa Rao K, Balaji B, Agarwal V. Design and Performance Analysis of High-k Gate All Around Fin-field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2024;37(3):476-83. 10.5829/ije.2024.37.03c.04
  5. Krishnamurthya A, Reddyb DV, Radhammac E, Jyothirmayeed B, Raoe DS, Agarwale V, et al. Design and Performance Analysis of 6H-SiC Metal-Semiconductor Field-Effect Transistor with Undoped and Recessed Area under Gate in 10nm Technology. International Journal of Engineering, Transactions C: Aspects. 2023;36(12):2264-71. 10.5829/ije.2023.36.12c.16
  6. Buttol S, Balaji B, Srinivasa Rao K. Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology. International Journal of Engineering, Transactions A: Basics. 2024;37(4):588-95. 10.5829/ije.2024.37.04a.01
  7. Radhamma E, Vemana Chary D, Krishnamurthy A, Venkatarami Reddy D, Sreenivasa Rao D, Gowthami Y, et al. Performance analysis of high-k dielectric heterojunction high electron mobility transistor for rf applications. International Journal of Engineering, Transactions C: Aspects. 2023;36(9):1652-8. 10.5829/ije.2023.36.09c.09
  8. Gowthami Y, Balaji B, Srinivasa Rao K. Performance analysis and optimization of asymmetric front and back pi gates with dual material in gallium nitride high electron mobility transistor for nano electronics application. International Journal of Engineering, Transactions A: Basics 2023;36(7):1269-77. 10.5829/ije.2023.36.07a.08
  9. Howldar S, Balaji B, Srinivasa Rao K. Design and qualitative analysis of hetero dielectric tunnel field effect transistor device. International Journal of Engineering, Transactions C: Aspects. 2023;36(6):1129-35. 10.5829/ije.2023.36.06c.11
  10. Padmaja P, Vemana Chary D, Erigela R, Sirisha G, ChayaDevi S, Pedapudi MC, et al. Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications. International Journal of Engineering, Transactions C: Aspects. 2024;37(6):1059-66. 10.5829/ije.2024.37.06c.02
  11. Gowthami Y, Balaji B, Rao KS. Design and performance evaluation of 6nm hemt with silicon sapphire substrate. Silicon. 2022;14(17):11797-804. https://doi.org/10.1007/s12633-022-01900-7
  12. Kumar PK, Balaji B, Rao KS. Performance analysis of sub 10 nm regime source halo symmetric and asymmetric nanowire MOSFET with underlap engineering. Silicon. 2022;14(16):10423-36. https://doi.org/10.1007/s12633-022-01747-y
  13. Anvarifard MK, Orouji AA. Enhancement of a nanoscale novel Esaki tunneling diode source TFET (ETDS-TFET) for low-voltage operations. Silicon. 2019;11(6):2547-56. https://doi.org/10.1007/s12633-018-0043-6
  14. Dixit A, Gupta N. A compact model of gate capacitance in ballistic gate-all-around carbon nanotube field effect transistors. International Journal of Engineering, Transactions A: Basics. 2021;34(7):1718-24. 10.5829/IJE.2021.34.07A.16
  15. Raj A, Singh S, Priyadarshani KN, Arya R, Naugarhiya A. Vertically Extended Drain Double Gate S i 1− x G ex Source Tunnel FET: Proposal & Investigation For Optimized Device Performance. Silicon. 2021;13:2589-604. https://doi.org/10.1007/s12633-02000603-1
  16. Chakrabarty R, Roy S, Pathak T, Kumar Mandal N. Design of area efficient single bit comparator circuit using quantum dot cellular automata and its digital logic gates realization. International Journal of Engineering, Transactions C: Aspects. 2021;34(12):2672-8. 10.5829/ije.2021.34.12c.13
  17. Gopal G, Varma T. Simulation-based analysis of ultra thin-body double gate ferroelectric TFET for an enhanced electric performance. Silicon. 2022;14(12):6553-63. https://doi.org/10.1007/s12633-021-01428-2
  18. Roy A, Mitra R, Kundu A, editors. Influence of channel thickness on analog and RF performance enhancement of an underlap DG AlGaN/GaN based MOS-HEMT device. 2019 Devices for Integrated Circuit (DevIC); 2019: IEEE.
  19. Gedam A, Acharya B, Mishra GP. Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon. 2021;13:167-78. https://doi.org/10.1007/s12633-020-00410-8
  20. Hoonan Mehrabani A, Fattah A, Rahimi E. Design and simulation of a novel hetero-junction bipolar transistor with gate-controlled current gain. International Journal of Engineering, Transactions C: Aspects. 2023;36(3):433-40. 10.5829/ije.2023.36.03c.01
  21. Rafiee A, Nickabadi S, Nobarian M, Tagimalek H, Khatami H. Experimental investigation joining al 5083 and high-density polyethylen by protrusion friction stir spot welding containing nanoparticles using taguchi method. International Journal of Engineering, Transactions C: Aspects. 2022;35(6):1144-53. 10.5829/ije.2022.35.06c.06
  22. Alassery F, Khan AI, Shaik MS. Implementation of Advanced Tunnel Field Effect Transistor (DP-TFET) for High Power Switching Applications. Silicon. 2022;14(15):9589-93. https://doi.org/10.1007/s12633-021-01647-7
  23. Sahu SA, Goswami R, Mohapatra S. Characteristic enhancement of hetero dielectric DG TFET using SiGe pocket at source/channel interface: proposal and investigation. Silicon. 2020;12(3):513-20. https://doi.org/10.1007/s12633-019-00159-9
  24. Balaji B, Srinivasa Rao K, Girija Sravani K, Bindu Madhav N, Chandrahas K, Jaswanth B. Improved drain current characteristics of hfo2/sio2 dual material dual gate extension on drain side-tfet. Silicon. 2022;14(18):12567-72. https://doi.org/10.1007/s12633-022-01955-6
  25. Kumar PK, Balaji B, Rao KS. Halo-doped hetero dielectric nanowire mosfet scaled to the sub-10 nm node. Transactions on Electrical and Electronic Materials. 2023;24(4):303-13. https://doi.org/10.1007/s42341-023-00448-6
  26. Emami N, Kuchaki Rafsanjani M. Extreme learning machine based pattern classifiers for symbolic interval data. International Journal of Engineering, Transactions B: Applications. 2021;34(11):2545-56. 10.5829/IJE.2021.34.11B.17
  27. Fouladinia F, Gholami M. Decimal to excess-3 and excess-3 to decimal code converters in QCA nanotechnology. International Journal of Engineering, Transactions C: Aspects. 2023;36(9):1618-25. 10.5829/ije.2023.36.09c.05
  28. Gowthami Y, Balaji B, Rao KS. Design and analysis of a symmetrical Low-κ source-side spacer multi-gate Nanowire device. Journal of Electronic Materials. 2023;52(4):2561-8. https://doi.org/10.1007/s11664-023-10217-z
  29. Rani CSH, Bagan KB, Roach RS. Improved drain current characteristics of germanium source triple material double gate hetero-dielectric stacked TFET for low power applications. Silicon. 2021;13:2753-62. https://doi.org/10.1007/s12633-020-00556-5
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Articles in Press, Accepted Manuscript
Available Online from 01 September 2024

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