Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Document Type : Original Article

Authors

1 Department of Electronics and Communication Engineering, Teegala Krishna Reddy Engineering College, Meerpet, Hyderabad, India

2 Department of Electronics and Communication Engineering, Teegala Krishna Reddy Engineering College, Meerpet, Hyderabad, India-500097

3 Department of information Technology, Vasavi College of Engineering, Hyderabad, India

4 Department of Electronics and Communications Engineering, Vignan's Foundation for Science Technology & Research (Deemed to be University), Vadlamudi, Guntur District, A.P, India

5 Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh, India

Abstract

A High-K Dielectric Dual Metal Gate FinFET (DMG-FinFET) is proposed in this work to improve the drain current and electrical characteristics of the device. The proposed device employing dielectric materials such as Silicon dioxide, Hafnium oxide and Titanium oxide and investigated in 10 nm technology. The architecture represents a critical advancement in transistor design, addressing challenges posed by traditional high-K gate dielectric materials being HfO2 and TiO2. This work employs a comprehensive approach, incorporating simulation techniques to evaluate the performance metrics of DMG FinFET. This investigation encompasses key aspects being transistor characteristics, power consumption, and reliability. This high-k dielectric (HfO2) Dual material Gate –FinFET device achieving improved performance parameters such as Ion= 32.12 mA, Ioff= 33 μA, Gm(max) = 0.045 S, Gds(max) = 0.024 S and Ron(max) = 32.87 kΩ. Therefore this work is suitable for designing high performance devices with high-k dielectric materials being HfO2 and TiO2.  The impact of dual metal gate materials on Ion, Ioff, Gm (max), Gds(max) and Ron(max) is calculated and improved 64% compared to conventional device.

Graphical Abstract

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Keywords

Main Subjects

References

  1. Howldar S, Balaji B, Srinivasa Rao K. Design and Analysis of Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2023;36(12):2137-44. 10.5829/ije.2023.36.12c.01
  2. Krishnamurthya A, Reddyb DV, Radhammac E, Jyothirmayeed B, Raoe DS, Agarwale V, et al. Design and Performance Analysis of 6H-SiC Metal-Semiconductor Field-Effect Transistor with Undoped and Recessed Area under Gate in 10nm Technology. International Journal of Engineering, Transactions C: Aspects. 2023;36(12):2264-71. 10.5829/ije.2023.36.12c.16
  3. Mehrabani AH, Fattah A, Rahimi E. Design and Simulation of a Novel Hetero-junction Bipolar Transistor with Gate-Controlled Current Gain. International Journal of Engineering, Transactions C: Aspects. 2023;36(03):433. 10.5829/ije.2023.36.03c
  4. Rohith Sai K, Girija Sravani K, Srinivasa Rao K, Balaji B, Agarwal V. Design and Performance Analysis of High-k Gate All Around Fin-field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2024;37(3):476-83. 10.5829/ije.2024.37.03c.04
  5. Howldar S, Balaji B, Srinivasa Rao K. Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor. International Journal of Engineering, Transactions C: Aspects. 2024;37(3):520-8. 10.5829/ije.2024.37.03c.09
  6. Yadav S, Kumar H, Negi CMS. Extensive analysis of gate leakage current in nano-scale multi-gate MOSFETs. Transactions on Electrical and Electronic Materials. 2022;23(6):658-65. https://doi.org/10.1007/s42341-022-00404-w
  7. Kaur G, Gill SS, Rattan M. Lanthanum Doped Zirconium Oxide (LaZrO 2) High-k Gate Dielectric FinFET SRAM Cell Optimization. Transactions on Electrical and Electronic Materials. 2021:1-12. https://doi.org/10.1007/s42341-021-00296-2
  8. Radhamma E, Vemana Chary D, Krishnamurthy A, Venkatarami Reddy D, Sreenivasa Rao D, Gowthami Y, et al. Performance analysis of high-k dielectric heterojunction high electron mobility transistor for rf applications. International Journal of Engineering, Transactions C: Aspects. 2023;36(9):1652-8. 10.5829/ije.2023.36.09c.09
  9. Gowthami Y, Balaji B, Srinivasa Rao K. Performance Analysis and Optimization of Asymmetric Front and Back Pi Gates with Dual Material in Gallium Nitride High Electron Mobility Transistor for Nano Electronics Application. International Journal of Engineering, Transactions A: Basics 2023;36(7):1269-77. 10.5829/ije.2023.36.07a.08
  10. Raushan RK, Ansari MR, Chauhan U, Khalid M, Mohapatra B. Implementation of 12T and 14T SRAM bitcell using FinFET with optimized parameters. Transactions on Electrical and Electronic Materials. 2021;22:328-34. https://doi.org/10.1007/s42341-020-00243-7
  11. Chung H. Analysis of Electrical Characteristics of Shielded Gate Power MOSFET According to Design and Process Parameters. Transactions on Electrical and Electronic Materials. 2018;19:245-8. https://doi.org/10.1007/s42341-018-0049-1
  12. Gowthami Y, Balaji B, Rao KS. Design and performance evaluation of 6nm hemt with silicon sapphire substrate. Silicon. 2022;14(17):11797-804. https://doi.org/10.1007/s12633-022-01900-7
  13. Kumar PK, Balaji B, Rao KS. Performance analysis of sub 10 nm regime source halo symmetric and asymmetric nanowire MOSFET with underlap engineering. Silicon. 2022;14(16):10423-36. https://doi.org/10.1007/s12633-022-01747-y
  14. Howldar S, Balaji B, Srinivasa Rao K. Design and Qualitative Analysis of Hetero Dielectric Tunnel Field Effect Transistor Device. International Journal of Engineering, Transactions C: Aspects 2023;36(6):1129-35. 10.5829/ije.2023.36.06c.11
  15. Anvarifard MK, Orouji AA. Enhancement of a nanoscale novel Esaki tunneling diode source TFET (ETDS-TFET) for low-voltage operations. Silicon. 2019;11(6):2547-56. https://doi.org/10.1007/s12633-018-0043-6
  16. Dixit A, Gupta N. A compact model of gate capacitance in ballistic gate-all-around carbon nanotube field effect transistors. International Journal of Engineering, Transactions A: Basics. 2021;34(7):1718-24. 10.5829/IJE.2021.34.07A.16
  17. Sharma S, Chaujar R. Band gap and gate metal engineering of novel hetero-material InAs/GaAs-based JLTFET for improved wireless applications. Journal of Materials Science: Materials in Electronics. 2021;32(3):3155-66. https://doi.org/10.1007/s10854-020-05064-1
  18. Chakrabarty R, Roy S, Pathak T, Kumar Mandal N. Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization. International Journal of Engineering, Transactions C: Aspects. 2021;34(12):2672-8. 10.5829/ije.2021.34.12c.13
  19. Jaiswal NK, Ramakrishnan V. Vertical GaN reverse trench-gate power MOSFET and DC-DC converter. Transactions on Electrical and Electronic Materials. 2021;22:363-71. https://doi.org/10.1007/s42341-020-00248-2
  20. Roy A, Mitra R, Kundu A, editors. Influence of channel thickness on analog and RF performance enhancement of an underlap DG AlGaN/GaN based MOS-HEMT device. 2019 Devices for Integrated Circuit (DevIC); 2019: IEEE.
  21. Gedam A, Acharya B, Mishra GP. Junctionless silicon nanotube TFET for improved DC and radio frequency performance. Silicon. 2021;13:167-78. https://doi.org/10.1007/s12633-020-00410-8
  22. Mehrabani AH, Fattah A, Rahimi E. Design and Simulation of a Novel Hetero-junction Bipolar Transistor with Gate-Controlled Current Gain. International Journal of Engineering, Transactions C: Aspects 2023;36(03):433. 10.5829/ije.2023.36.03c.01
  23. Rafiee A, Nickabadi S, Nobarian M, Tagimalek H, Khatami H. Experimental investigation joining al 5083 and high-density polyethylen by protrusion friction stir spot welding containing nanoparticles using taguchi method. International Journal of Engineering, Transactions C: Aspects. 2022;35(6):1144-53. 10.5829/ije.2022.35.06c.06
  24. Misra S, Biswal SM, Baral B, Pati SK. Study of DC and Analog/RF Performances Analysis of Short Channel Surrounded Gate Junctionless Graded Channel Gate Stack MOSFET. Transactions on Electrical and Electronic Materials. 2023:1-10. https://doi.org/10.1007/s42341-023-00455-7
  25. Sahu SA, Goswami R, Mohapatra S. Characteristic enhancement of hetero dielectric DG TFET using SiGe pocket at source/channel interface: proposal and investigation. Silicon. 2020;12(3):513-20. https://doi.org/10.1007/s12633-019-00159-9
  26. Balaji B, Srinivasa Rao K, Girija Sravani K, Bindu Madhav N, Chandrahas K, Jaswanth B. Improved drain current characteristics of hfo2/sio2 dual material dual gate extension on drain side-tfet. Silicon. 2022;14(18):12567-72. https://doi.org/10.1007/s12633-022-01955-6
  27. Kumar PK, Balaji B, Rao KS. Halo-Doped Hetero Dielectric Nanowire MOSFET Scaled to the Sub-10 nm Node. Transactions on Electrical and Electronic Materials. 2023:1-11. https://doi.org/10.1007/s42341-023-00448-6
  28. Emami N, Kuchaki Rafsanjani M. Extreme learning machine based pattern classifiers for symbolic interval data. International Journal of Engineering, Transactions B: Applications. 2021;34(11):2545-56. 10.5829/IJE.2021.34.11B.17
  29. Fouladinia F, Gholami M. Decimal to excess-3 and excess-3 to decimal code converters in QCA nanotechnology. International Journal of Engineering, Transactions C: Aspects. 2023;36(9):1618-25. 10.5829/ije.2023.36.09c.05
  30. Gowthami Y, Balaji B, Rao KS. Design and Analysis of a Symmetrical Low-κ Source-Side Spacer Multi-gate Nanowire Device. Journal of Electronic Materials. 2023;52(4):2561-8. https://doi.org/10.1007/s11664-023-10217-z
International Journal of Engineering
Volume 37, Issue 6
TRANSACTIONS C: Aspects
June 2024
Pages 1059-1066

Files

Share

How to cite

Statistics