Design and Performance Analysis of High-k Gate All Around Fin-field Effect Transistor

Document Type : Original Article

Authors

Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Andhra Pradesh, India

Abstract

This paper introduces and investigates a symmetrical structural design centered around a Nanoscale Fin Field-Effect Transistor (Fin-FET). Employing advanced tcad simulation techniques, the study discusses the characteristics of the Fin-FET. Here, a comprehensive exploration of the device performance across a spectrum of parameters, including drain current, electric field distribution, surface potential variations, energy band configurations, carrier concentration behaviors, and the Ion/Ioff ratio. Through rigorous analysis, the research sheds light on the symmetrical design's impact on these fundamental aspects of the Fin-FET's operation. The insights gained from this study hold the potential to enhance our understanding of device behavior, paving the road for refined designs and optimized utilization of Fin-FET technology in advanced semiconductor applications. Several types of engineering's are applied to test the device under various aspects. Gate engineering, doping engineering, and work function engineering were applied to test the device drain current characteristics. Therefore, this proposed has been widely adopted in modern Nano scale semiconductor devices.

Graphical Abstract

Design and Performance Analysis of High-k Gate All Around Fin-field Effect Transistor

Keywords

Main Subjects

References

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International Journal of Engineering
Volume 37, Issue 3
TRANSACTIONS C: Aspects
March 2024
Pages 476-483

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